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ds05-20911-1e fujitsu semiconductor data sheet flash memory cmos 8 m (1 m 8/512 k 16) bit mbm29sl800te/be -90 / 10 n description the mbm29sl800te/be are a 8 m-bit, 1.8 v-only flash memory organized as 1 mbytes of 8 bits each or 512 kwords of 16 bits each. the mbm29sl800te/be are offered in a 48-ball fbga and 45-ball scsp packages. these devices are designed to be programmed in-system with the standard system 1.8 v v cc supply. 12.0 v v pp and 5.0 v v cc are not required for write or erase operations. the devices can also be reprogrammed in standard eprom programmers. (continued) n product line up n packages part no. mbm29sl800te/be-90 mbm29sl800te/be-10 v cc 1.65 v to 1.95 v max address access time 90 ns 100 ns max ce access time 90 ns 100 ns max oe access time 30 ns 35 ns 48-ball plastic fbga 45-ball plastic scsp (bga-48p-m20) (wlp-45p-m02)
mbm29sl800te/be -90/10 2 (continued) the standard mbm29sl800te/be offer access times 90 ns and 100 ns, allowing operation of high-speed microprocessors without wait states. to eliminate bus contention the devices have separate chip enable (ce ) , write enable (we ) , and output enable (oe ) controls. the device supports pin and command set compatible with jedec standard e 2 proms. commands are written to the command register using standard microprocessor write timings. register contents serve as input to an internal state-machine which controls the erase and programming circuitry. write cycles also internally latch addresses and data needed for the programming and erase operations. reading data out of the devices is similar to reading from 5.0 v and 12.0 v flash or eprom devices. the device is programmed by executing the program command sequence. this will invoke the embedded program algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. typically, each sector can be programmed and verified in about 0.5 seconds. erase is accomplished by executing the erase command sequence. this will invoke the embedded erase algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. during erase, the devices automatically time the erase pulse widths and verify proper cell margin. each sector is typically erased and verified in 1.5 second. (if already completely preprogrammed.) the devices also feature a sector erase architecture. the sector mode allows each sector to be erased and reprogrammed without affecting other sectors. the mbm29sl800te/be are erased when shipped from the factory. the devices feature single 1.8 v power supply operation for both read and write functions. internally generated and regulated voltages are provided for the program and erase operations. a low v cc detector automatically inhibits write operations on the loss of power. the end of program or erase is detected by data polling of dq 7 , by the toggle bit feature on dq 6 , or the ry/by output pin. once the end of a program or erase cycle has been completed, the device internally returns to the read mode. fujitsus flash technology combines years of flash memory manufacturing experience to produce the highest levels of quality, reliability, and cost effectiveness. the mbm29sl800te/be memories electrically erase the entire chip or all bits within a sector simultaneously via fowler-nordhiem tunneling. the bytes/words are pro- grammed one byte/word at a time using the eprom programming mechanism of hot electron injection.
mbm29sl800te/be -90/10 3 n features ? 0.23 m m m m m process technology ? single 1.8 v read , program , and erase minimizes system level power requirements ? compatible with jedec - standard world - wide pinouts 48-ball fbga (package suffix : pbt) 45-ball scsp (package suffix : pw) ? minimum 100,000 program / erase cycles ? high performance 90 ns maximum access time ? sector erase architecture one 8 kword, two 4 kwords, one 16 kword, and fifteen 32 kwords sectors in word mode one 16 kbyte, two 8 kbytes, one 32 kbyte, and fifteen 64 kbytes sectors in byte mode any combination of sectors can be concurrently erased. also supports full chip erase ? boot code sector architecture t = top sector b = bottom sector ? embedded erase tm algorithms automatically pre-programs and erases the chip or any sector ? embedded program tm algorithms automatically writes and verifies data at specified address ?data polling and toggle bit feature for detection of program or erase cycle completion ? ready / busy output ( ry / by ) hardware method for detection of program or erase cycle completion ? automatic sleep mode when addresses remain stable, automatically switch themselves to low power mode ? erase suspend / resume suspends the erase operation to allow a read in another sector within the same device ? sector protection hardware method disables any combination of sectors from program or erase operations ? sector protection set function by extended sector protect command ? fast programming function by extended command ? temporary sector unprotection temporary sector unprotection via the reset pin embedded erase tm and embedded program tm are trademarks of advanced micro devices, inc.
mbm29sl800te/be -90/10 4 n pin assignments a6 b6 c6 d6 e6 f6 g6 h6 a 13 a 12 a 14 a 15 a 16 dq 15 /a -1 v ss a5 b5 c5 d5 e5 f5 g5 h5 a 9 a 8 a 10 a 11 dq 7 dq 14 dq 13 dq 6 a4 b4 c4 d4 e4 f4 g4 h4 we reset n.c. n.c. dq 5 dq 12 v cc dq 4 a3 b3 c3 d3 e3 f3 g3 h3 ry/by n.c. a 18 n.c. dq 2 dq 10 dq 11 dq 3 a2 b2 c2 d2 e2 f2 g2 h2 a 7 a 17 a 6 a 5 dq 0 dq 8 dq 9 dq 1 a1 b1 c1 d1 e1 f1 g1 h1 a 3 a 4 a 2 a 1 a 0 ce oe v ss byte a 3 a 4 a 7 a 17 a 6 a 5 dq 0 dq 8 dq 9 dq 1 ry/by a 18 dq 2 dq 10 dq 11 dq 3 we reset n.c. dq 5 dq 12 v cc dq 4 a 9 a 8 a 10 a 11 dq 7 dq 14 dq 13 dq 6 a 13 a 12 b5 c5 d5 e5 f5 g5 h5 b4 c4 d4 e4 f4 g4 h4 a 0 a3 b3 c3 d3 e3 f3 g3 h3 a 1 a2 b2 c2 d2 e2 f2 g2 h2 a 2 a1 b1 c1 d1 e1 f1 g1 h1 byte j5 v ss j4 a 16 j3 a 15 j2 a 14 j1 dq 15 /a -1 a5 ce oe a4 v ss (wlp-45p-m02) scsp (top view) marking side fbga (top view) marking side (bga-48p-m20)
mbm29sl800te/be -90/10 5 n pin description pin name function a 18 to a 0 , a- 1 address inputs dq 15 to dq 0 data inputs/outputs ce chip enable oe output enable we write enable reset hardware reset ry/by ready/busy output byte selects 8-bit or 16-bit mode v cc device power supply v ss device ground n.c. no internal connection
mbm29sl800te/be -90/10 6 n block diagram n logic symbol a -1 v ss v cc we ce a 18 to a 0 oe dq 15 to dq 0 input/output buffers byte reset ry/by stb stb ry/by buffer erase voltage generator program voltage generator timer for program/erase low v cc detector chip enable output enable logic state control command register data latch y-gating cell matrix y-decoder x-decoder address latch 19 a 18 to a 0 we oe ce dq 15 to dq 0 16 or 8 byte reset a -1 ry/by
mbm29sl800te/be -90/10 7 n device bus operation mbm29sl800te/be user bus operations (byte = = = = v ih ) legend : l = v il , h = v ih , x = v il or v ih , see n dc characteristics. *1: manufacturer and device codes may also be accessed via a command register write sequence. see mbm29sl800te/be standard command definitions. *2: refer to the section on sector protection. *3: we can be v il if oe is v il , oe at v ih initiates the write operations. *4: v cc = 1.8 v 0.15v *5: it is also used for the extended sector protection. mbm29sl800te/be user bus operations (byte = = = = v il ) legend : l = v il , h = v ih , x = v il or v ih , see n dc characteristics. *1: manufacturer and device codes may also be accessed via a command register write sequence. see mbm29sl800te/be standard command definitions. *2: refer to the section on sector protection. *3: we can be v il if oe is v il , oe at v ih initiates the write operations. *4: v cc = 1.8 v 0.15 v *5: it is also used for the extended sector protection. operation ce oe we a 0 a 1 a 6 a 9 dq 15 to dq 0 reset standby h x x x x x x high-z h autoselect manufacturer code * 1 llhlllv id code h autoselect device code * 1 llhhllv id code h read * 3 llha 0 a 1 a 6 a 9 d out h output disable l h h x x x x high-z h write l h l a 0 a 1 a 6 a 9 d in h enable sector protection * 2, * 4 lhllhlx x v id verify sector protection * 2, * 4 llhlhlv id code h temporary sector unprotection * 5 xxxxxxx x v id reset (hardware) /standby xxxxxxx high-z l operation ce oe we dq 15 / a -1 a 0 a 1 a 6 a 9 dq 7 to dq 0 reset standby h x x x xxxxhigh-z h autoselect manufacturer code * 1 llhllllv id code h autoselect device code * 1 llhlhllv id code h read * 3 llha- 1 a 0 a 1 a 6 a 9 d out h output disable lhhxxxxxhigh-z h write l h l a- 1 a 0 a 1 a 6 a 9 d in h enable sector protection * 2, * 4 lhl l lhlv id xv id verify sector protection * 2, * 4 llhllhlv id code h temporary sector unprotection * 5 xxxxxxxx x v id reset (hardware) /standby x x x x xxxxhigh-z l
mbm29sl800te/be -90/10 8 mbm29sl800te/be standard command definitions *1 (continued) command sequence bus write cycles reqd first bus write cycle second bus write cycle third bus write cycle fourth bus read/write cycle fifth bus write cycle sixth bus write cycle addr. data addr. data addr. data addr. data addr. data addr. data reset * 2 word 1 xxxh f0h ?????????? byte reset * 2 word 3 555h aah 2aah 55h 555h f0h ra rd ???? byte aaah 555h aaah autoselect word 3 555h aah 2aah 55h 555h 90h 00h 04h ???? byte aaah 555h aaah program word 4 555h aah 2aah 55h 555h a0h pa pd ???? byte aaah 555h aaah chip erase word 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h byte aaah 555h aaah aaah 555h aaah sector erase word 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h sa 30h byte aaah 555h aaah aaah 555h sector erase suspend * 3 erase can be suspended during sector erase with addr. (h or l) . data (b0h) sector erase resume * 3 erase can be resumed after sector erase suspend with addr. (h or l) . data (30h) set to fast mode * 4 word 3 555h aah 2aah 55h 555h 20h ?????? byte aaah 555h aaah fast program * 4 word 2 xxxh a0h pa pd ???????? byte xxxh rest from fast mode * 5 word 2 xxxh 90h xxxh 00h * 8 ???????? byte xxxh xxxh extended sector protect * 6, * 7 word 4 xxxh 60h spa 60h spa 40h spa sd ???? byte
mbm29sl800te/be -90/10 9 (continued) *1 : the command combinations not described in mbm29sl800te/be standard command definitions are illegal. *2 : both reset commands are functionally equivalent, resetting the device to the read mode. *3 : the erase suspend and erase resume command are valid only during a sector erase operation. *4 : the set to fast mode command is required prior to the fast programming command. *5 : the reset from fast mode command is required to return to the read mode when the device is in fast mode. *6 : set sector address (sa) with (a 6 , a 1 , a 0 ) = (0, 1, 0). *7: this command is valid while reset =v id . *8 : the data f0h is also acceptable. notes : address bits a 18 to a 11 = x = h or l for all address commands except for program address (pa) and sector address (sa) bus operations are defined in mbm29sl800te/be user bus operations (byte = v ih ) and mbm29sl800te/be user bus operations (byte = v il ) in n device bus operation. ra = address of the memory location to be read pa = address of the memory location to be programmed addresses are latched on the falling edge of the we pulse. sa = address of the sector to be erased. the combination of a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 will uniquely select any sector. spa = sector address to be protected. set sector address (sa) and (a 6 , a 1 , a 0 ) = (0, 1, 0) rd = data read from location ra during read operation. pd = data to be programmed at location pa. data is latched on the rising edge of we . the system should generate the following address patterns : word mode : 555h or 2aah to addresses a 10 to a 0 byte mode : aaah or 555h to addresses a 10 to a 0 and a- 1 sd = sector protection verify data. output 01h at protected sector address and output 00h at unprotected sector address.
mbm29sl800te/be -90/10 10 mbm29sl800te/be sector protection verify autoselect codes *1 : a- 1 is for byte mode. at byte mode, dq 14 to dq 8 are high-z and dq 15 a -1 , the lowest address. *2 : outputs 01h at protected sector address and outputs 00h at unprotected sector address. extended autoselect code (b) : byte mode (w) : word mode hi-z : high-z * : at byte mode, dq 14 to dq 8 are high-z and dq 15 is a -1 , the lowest address. type a 18 to a 12 a 6 a 1 a 0 a- 1 * 1 code (hex) manufactures code x v il v il v il v il 04h device code mbm29sl800te byte xv il v il v ih v il eah word x 22eah mbm29sl800be byte xv il v il v ih v il 6bh word x 226bh sector protection sector address v il v ih v il v il 01h* 2 type code dq 15 dq 14 dq 13 dq 12 dq 11 dq 10 dq 9 dq 8 dq 7 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 manufactures code 04h a- 1 /0 0 0 0 0 0 0000000100 device code mbm29s l800te (b) * eah a- 1 hi-z hi-z hi-z hi-z hi-z hi-z hi-z 11101010 (w) 22eah 0 0 1 0 0 0 1011101010 mbm29s l800be (b) * 6bh a- 1 hi-z hi-z hi-z hi-z hi-z hi-z hi-z 01101011 (w) 226bh 0 0 1 0 0 0 1001101011 sector protection 01h a- 1 /0 0 0 0 0 0 0000000001
mbm29sl800te/be -90/10 11 n flexible sector - erase architecture ? one 16 kbyte, two 8 kbytes, one 32 kbyte, and fifteen 64 kbytes ? individual-sector, multiple-sector, or bulk-erase capability ? individual or multiple-sector protection is user definable. fffffh fbfffh f9fffh f7fffh effffh dffffh cffffh bffffh affffh 9ffffh 8ffffh 7ffffh 6ffffh 5ffffh 4ffffh 3ffffh 2ffffh 1ffffh 0ffffh 00000h fffffh effffh dffffh cffffh bffffh affffh 9ffffh 8ffffh 7ffffh 6ffffh 5ffffh 4ffffh 3ffffh 2ffffh 1ffffh 0ffffh 07fffh 05fffh 03fffh 00000h 7ffffh 7dfffh 7cfffh 7bfffh 77fffh 6ffffh 67fffh 5ffffh 57fffh 4ffffh 47fffh 3ffffh 37fffh 2ffffh 27fffh 1ffffh 17fffh 0ffffh 07fffh 00000h 7ffffh 77fffh 6ffffh 67fffh 5ffffh 57fffh 4ffffh 47fffh 3ffffh 37fffh 2ffffh 27fffh 1ffffh 17fffh 0ffffh 07fffh 03fffh 02fffh 01fffh 00000h 16 kbyte 8 kbyte 8 kbyte 32 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte 32 kbyte 8 kbyte 8 kbyte 16 kbyte ( 8) ( 16) ( 8) ( 16) mbm29sl800te sector architecture mbm29sl800be sector architecture
mbm29sl800te/be -90/10 12 sector address tables (mbm29sl800te) sector address a 18 a 17 a 16 a 15 a 14 a 13 a 12 address range ( 8) address range ( 16) sa0 0000xxx 00000h to 0ffffh 00000h to 07fffh sa1 0001xxx 10000h to 1ffffh 08000h to 0ffffh sa2 0010xxx 20000h to 2ffffh 10000h to 17fffh sa3 0011xxx 30000h to 3ffffh 18000h to 1ffffh sa4 0100xxx 40000h to 4ffffh 20000h to 27fffh sa5 0101xxx 50000h to 5ffffh 28000h to 2ffffh sa6 0110xxx 60000h to 6ffffh 30000h to 37fffh sa7 0111xxx 70000h to 7ffffh 38000h to 3ffffh sa8 1000xxx 80000h to 8ffffh 40000h to 47fffh sa9 1001xxx 90000h to 9ffffh 48000h to 4ffffh sa10 1010xxxa0000h to affffh 50000h to 57fffh sa11 1011xxxb0000h to bffffh 58000h to 5ffffh sa12 1100xxxc0000h to cffffh 60000h to 67fffh sa13 1101xxxd0000h to dffffh 68000h to 6ffffh sa14 1110xxxe0000h to effffh 70000h to 77fffh sa15 11110xxf0000h to f7fffh78 000h to 7bfffh sa16 1111100f8000h to f9fffh7c000h to 7cfffh sa17 1111101fa000h to fbfffh7d000h to 7dfffh sa18 111111xfc 000h to fffffh 7e000h to 7ffffh
mbm29sl800te/be -90/10 13 sector address tables (mbm29sl800be) sector address a 18 a 17 a 16 a 15 a 14 a 13 a 12 address range ( 8) address range ( 16) sa0 000000x 00000h to 03fffh 00000h to 01fffh sa1 0000010 04000h to 05fffh 02000h to 02fffh sa2 0000011 06000h to 07fffh 03000h to 03fffh sa3 00001xx 08000h to 0ffffh 04000h to 07fffh sa4 0001xxx 10000h to 1ffffh 08000h to 0ffffh sa5 0010xxx 20000h to 2ffffh 10000h to 17fffh sa6 0011xxx 30000h to 3ffffh 18000h to 1ffffh sa7 0100xxx 40000h to 4ffffh 20000h to 27fffh sa8 0101xxx 50000h to 5ffffh 28000h to 2ffffh sa9 0110xxx 60000h to 6ffffh 30000h to 37fffh sa10 0111xxx 70000h to 7ffffh 38000h to 3ffffh sa11 1000xxx 80000h to 8ffffh 40000h to 47fffh sa12 1001xxx 90000h to 9ffffh 48000h to 4ffffh sa13 1010xxxa0000h to affffh 50000h to 57fffh sa14 1011xxxb0000h to bffffh 58000h to 5ffffh sa15 1100xxxc0000h to cffffh 60000h to 67fffh sa16 1101xxxd0000h to dffffh 68000h to 6ffffh sa17 1110xxxe0000h to effffh 70000h to 77fffh sa18 1111xxxf0000h to fffffh 78000h to 7ffffh
mbm29sl800te/be -90/10 14 n functional description standby mode there are two ways to implement the standby mode on the mbm29sl800td/bd devices, one using both the ce and reset pins; the other via the reset pin only. when using both pins, a cmos standby mode is achieved with ce and reset inputs both held at v cc 0.3 v. under this condition the current consumed is less than 5 m a. the device can be read with standard access time (t ce ) from either of these standby modes. during embedded algorithm operation, v cc active current (i cc2 ) is required even ce = h. when using the reset pin only, a cmos standby mode is achieved with reset input held at v ss 0.3 v (ce = h or l) . under this condition the current is consumed is less than 5 m a. once the reset pin is taken high, the device requires t rh of wake up time before outputs are valid for read access. in the standby mode the outputs are in the high impedance state, independent of the oe input. automatic sleep mode there is a function called automatic sleep mode to restrain power consumption during read-out of mbm29sl800te/be data. this mode can be used effectively with an application requested low power consump- tion such as handy terminals. to activate this mode, mbm29sl800te/be automatically switch themselves to low power mode when mbm29sl800te/be addresses remain stably during access fine of 150 ns. it is not necessary to control ce , we , and oe on the mode. under the mode, the current consumed is typically 1 m a (cmos level) . since the data are latched during this mode, the data are read-out continuously. if the addresses are changed, the mode is canceled automatically and mbm29sl800te/be read-out the data for changed addresses. autoselect the autoselect mode allows the reading out of a binary code from the devices and will identify its manufacturer and type. this mode is intended for use by programming equipment for the purpose of automatically matching the devices to be programmed with its corresponding programming algorithm. this mode is functional over the entire temperature range of the devices. to activate this mode, the programming equipment must force v id (10 v to 11 v) on address pin a 9 . two identifier bytes may then be sequenced from the devices outputs by toggling address a 0 from v il to v ih . all addresses are dont cares except a 0 , a 1 , a 6 , and a- 1 . (see mbm29sl800te/be sector protection verify autoselect codes in n device bus operation.) the manufacturer and device codes may also be read via the command register, for instances when the mbm29sl800te/be are erased or programmed in a system without access to high voltage on the a 9 pin. the command sequence is illustrated in mbm29sl800te/be standard command definitions in n device bus operation. (refer to autoselect command section.) byte 0 (a 0 = v il ) represents the manufacturers code (fujitsu = 04h) and (a 0 = v ih ) represents the device identifier code (mbm29sl800te = eah and mbm29sl800be = 6bh for 8 mode; mbm29sl800te = 22eah and mbm29sl800be = 226bh for 16 mode) . these two bytes/words are given in mbm29lv800te/be sector protection verify autoselect codes table and extended autoselect code table in n device bus operation. all identifiers for manufactures and device will exhibit odd parity with dq 7 defined as the parity bit. in order to read the proper device codes when executing the autoselect, a 1 must be v il . (see mbm29sl800te/be sector protection verify autoselect codes and extended autoselect code in n device bus operation.) read mode the mbm29sl800te/be have two control functions which must be satisfied in order to obtain data at the outputs. ce is the power control and should be used for a device selection. oe is the output control and should be used to gate data to the output pins if a device is selected. address access time (t acc ) is equal to the delay from stable addresses to valid output data. the chip enable access time (t ce ) is the delay from stable addresses and stable ce to valid data at the output pins. the output enable access time is the delay from the falling edge of oe to valid data at the output pins. (assuming the addresses have been stable for at least t acc -t oe time.) when reading out a data without changing addresses after power-up, it is necessary to input hardware reset or change ce pin from h to l
mbm29sl800te/be -90/10 15 output disable with the oe input at a logic high level (v ih ) , output from the devices are disabled. this will cause the output pins to be in a high impedance state. write device erasure and programming are accomplished via the command register. the contents of the register serve as inputs to the internal state machine. the state machine outputs dictate the function of the device. the command register itself does not occupy any addressable memory location. the register is a latch used to store the commands, along with the address and data information needed to execute the command. the com- mand register is written by bringing we to v il , while ce is at v il and oe is at v ih . addresses are latched on the falling edge of we or ce , whichever happens later; while data is latched on the rising edge of we or ce , whichever happens first. standard microprocessor write timings are used. refer to ac write characteristics and the erase/programming waveforms for specific timing parameters. sector protection the mbm29sl800te/be feature hardware sector protection. this feature will disable both program and erase operations in any number of sectors (0 through 18) . the sector protection feature is enabled using programming equipment at the users site. the devices are shipped with all sectors unprotected. to activate this mode, the programming equipment must force v id on address pin a 9 and control pin oe , ce = v il , and a 6 = v il . the sector addresses (a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 ) should be set to the sector to be protected. sector address tables (mbm29sl800te) and sector address tables (mbm29sl800te) in n flexible sector-erase architecture define the sector address for each of the nineteen (19) indi- vidual sectors. programming of the protection circuitry begins on the falling edge of the we pulse and is terminated with the rising edge of the same. sector addresses must be held constant during the we pulse. see sector protection timing diagram in n timing diagram and sector protection algorithm in n flow chart for sector pro- tection waveforms and algorithm. to verify programming of the protection circuitry, the programming equipment must force v id on address pin a 9 with ce and oe at v il and we at v ih . scanning the sector addresses (a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 ) while (a 6 , a 1 , a 0 ) = (0, 1, 0) will produce a logical 1 code at device output dq 0 for a protected sector. otherwise the devices will read 00h for unprotected sector. in this mode, the lower order addresses, except for a 0 , a 1 , and a 6 are dont cares. address locations with a 1 = v il are reserved for autoselect manufacturer and device codes. a- 1 requires to apply to v il on byte mode. temporary sector unprotection this feature allows temporary unprotection of previously protected sectors of the mbm29sl800te/be devices in order to change data. the sector unprotection mode is activated by setting the reset pin to high voltage (v id ) . during this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. once the v id is taken away from the reset pin, all the previously protected sectors will be protected again. see temporary sector unprotection timing diagram in n timing diagram and temporary sector unprotection algorithm in n flow chart. reset hardware reset the mbm29sl800te/be devices may be reset by driving the reset pin to v il . the reset pin has a pulse requirement and has to be kept low (v il ) for at least 500 ns in order to properly reset the internal state machine. any operation in the process of being executed will be terminated and the internal state machine will be reset to the read mode 20 m s after the reset pin is driven low. furthermore, once the reset pin goes high, the devices require an additional t rh before it will allow read access. when the reset pin is low, the devices will be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. if a hardware reset occurs during a program or erase operation, the data at that particular location will be corrupted. please note that the ry/by output signal should be ignored during the reset pulse. see reset , ry/by timing diagram in n timing diagram for the timing diagram. refer to temporary sector unprotection for additional functionality.
mbm29sl800te/be -90/10 16 n command definitions device operations are selected by writing specific address and data sequences into the command register. mbm29sl800te/be standard command definitions in n device bus operation defines the valid register command sequences. note that the erase suspend (b0h) and erase resume (30h) commands are valid only while the sector erase operation is in progress. moreover both reset commands are functionally equivalent, resetting the device to the read mode. please note that commands are always written at dq 7 to dq 0 and dq 15 to dq 8 bits are ignored. reset command in order to return from autoselect mode or exceeded timing limits (dq 5 = 1) to read mode, the reset operation is initiated by writing the reset command sequence into the command register. the device remains enabled for reads until the command register contents are altered. the device will automatically power-up in the reset state. in this case, a command sequence is not required to read data. autoselect command flash memories are intended for use in applications where the local cpu alters memory contents. as such, manufacture and device codes must be accessible while the devices reside in the target system. prom pro- grammers typically access the signature codes by raising a 9 to a high voltage. however, multiplexing high voltage onto the address lines is not generally desired system design practice. the device contains an autoselect command operation to supplement traditional prom programming method- ology. the operation is initiated by writing the autoselect command sequence into the command register. following the command write, a read cycle from address xx00h retrieves the manufacture code of 04h. a read cycle from address xx01h for 16 (xx02h for 8) returns the device code (mbm29sl800te = eah and mbm29sl800be = 6bh for 8 mode; mbm29sl800te = 22eah and mbm29sl800be = 226bh for 16 mode) . (see mbm29sl800te/be sector protection verify autoselect codes and extended autoselect code in n device bus operation.) all manufacturer and device codes will exhibit odd parity with dq 7 defined as the parity bit. sector state (protection or unprotection) will be informed by address xx02h for 16 (xx04h for 8) . scanning the sector addresses (a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 ) while (a 6 , a 1 , a 0 ) = (0, 1, 0) will produce a logical 1 at device output dq 0 for a protected sector. the programming verification should be perform margin mode on the protected sector. (see mbm29sl800te/be user bus operations (byte = v ih ) and mbm29sl800te/be user bus operations (byte = v il ) in n device bus operation.) to terminate the operation, it is necessary to write the reset command sequence into the register, and also to write the autoselect command during the operation, execute it after writing reset command sequence. byte/word programming the devices are programmed on a byte-by-byte (or word-by-word) basis. programming is a four bus cycle operation. there are two unlock write cycles. these are followed by the program set-up command and data write cycles. addresses are latched on the falling edge of ce or we , whichever happens later and the data is latched on the rising edge of ce or we , whichever happens first. the rising edge of ce or we (whichever happens first) begins programming. upon executing the embedded program algorithm command sequence, the system is not required to provide further controls or timings. the device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. the automatic programming operation is completed when the data on dq 7 is equivalent to data written to this bit at which time the devices return to the read mode and addresses are no longer latched. (see hardware sequence flags.) therefore, the devices require that a valid address to the devices be supplied by the system at this particular instance of time. hence, data polling must be performed at the memory location which is being programmed. if hardware reset occurs during the programming operation, it is impossible to guarantee the data are being written.
mbm29sl800te/be -90/10 17 programming is allowed in any sequence and across sector boundaries. beware that a data 0 cannot be programmed back to a 1. attempting to do so may either hang up the device or result in an apparent success according to the data polling algorithm but a read from read/reset mode will show that the data is still 0. only erase operations can convert 0s to 1s. embedded program tm algorithm in n flow chart illustrates the embedded program tm algorithm using typical command strings and bus operations. chip erase chip erase is a six bus cycle operation. there are two unlock write cycles. these are followed by writing the set-up command. two more unlock write cycles are then followed by the chip erase command. chip erase does not require the user to program the device prior to erase. upon executing the embedded erase algorithm command sequence the devices will automatically program and verify the entire memory for an all zero data pattern prior to electrical erase (preprogram function) . the system is not required to provide any controls or timings during these operations. the automatic erase begins on the rising edge of the last we pulse in the command sequence and terminates when the data on dq 7 is 1 (see write operation status section.) at which time the device returns to read the mode. chip erase time; sector erase time all sectors + chip program time (preprogramming) embedded erase tm algorithm in n flow chart illustrates the embedded erase tm algorithm using typical command strings and bus operations. sector erase sector erase is a six bus cycle operation. there are two unlock write cycles. these are followed by writing the set-up command. two more unlock write cycles are then followed by the sector erase command. the sector address (any address location within the desired sector) is latched on the falling edge of we , while the command (data = 30h) is latched on the rising edge of we . after time-out of 50 m s from the rising edge of the last sector erase command, the sector erase operation will begin. multiple sectors may be erased concurrently by writing the six bus cycle operations on mbm29sl800te/be standard command definitions in n device bus operation. this sequence is followed with writes of the sector erase command to addresses in other sectors desired to be concurrently erased. the time between writes must be less than 50 m s otherwise that command will not be accepted and erasure will start. it is recom- mended that processor interrupts be disabled during this time to guarantee this condition. the interrupts can be re-enabled after the last sector erase command is written. a time-out of 50 m s from the rising edge of the last we will initiate the execution of the sector erase command (s) . if another falling edge of the we occurs within the 50 m s time-out window the timer is reset. (monitor dq 3 to determine if the sector erase timer window is still open, see section dq 3 , sector erase timer.) resetting the devices once execution has begun will corrupt the data in the sector. in that case, restart the erase on those sectors and allow them to complete. (refer to the write operation status section for sector erase timer operation.) loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 18) . sector erase does not require the user to program the devices prior to erase. the devices automatically program all memory locations in the sector (s) to be erased prior to electrical erase (preprogram function) . when erasing a sector or sectors the remaining unselected sectors are not affected. the system is not required to provide any controls or timings during these operations. the automatic sector erase begins after the 50 m s time out from the rising edge of the we pulse for the last sector erase command pulse and terminates when the data on dq 7 is 1 (see write operation status section.) at which time the devices return to the read mode. data polling must be performed at an address within any of the sectors being erased. multiple sector erase time; [sector erase time + sector program time (preprogram- ming) ] number of sector erase embedded erase tm algorithm in n flow chart illustrates the embedded erase tm algorithm using typical command strings and bus operations.
mbm29sl800te/be -90/10 18 erase suspend/resume the erase suspend command allows the user to interrupt a sector erase operation and then perform data reads from or programs to a sector not being erased. this command is applicable only during the sector erase operation which includes the time-out period for sector erase. writting the erase suspend command during the sector erase time-out results in immediate termination of the time-out period and suspension of the erase operation. writing the erase resume command resumes the erase operation. the addresses are dont cares when writing the erase suspend or erase resume command. when the erase suspend command is written during the sector erase operation, the device will take a maximum of 20 m s to suspend the erase operation. when the devices have entered the erase-suspended mode, the ry/by output pin and the dq 7 bit will be at logic 1, and dq 6 will stop toggling. the user must use the address of the erasing sector for reading dq 6 and dq 7 to determine if the erase operation has been suspended. further writes of the erase suspend command are ignored. when the erase operation has been suspended, the devices default to the erase-suspend-read mode. reading data in this mode is the same as reading from the standard read mode except that the data must be read from sectors that have not been erase-suspended. successively reading from the erase-suspended sector while the device is in the erase-suspend-read mode will cause dq 2 to toggle. (see the section on dq 2 .) after entering the erase-suspend-read mode, the user can program the device by writing the appropriate com- mand sequence for program. this program mode is known as the erase-suspend-program mode. again, pro- gramming in this mode is the same as programming in the regular program mode except that the data must be programmed to sectors that are not erase-suspended. successively reading from the erase-suspended sector while the devices are in the erase-suspend-program mode will cause dq 2 to toggle. the end of the erase- suspended program operation is detected by the ry/by output pin, data polling of dq 7 , or by the toggle bit i (dq 6 ) which is the same as the regular program operation. note that dq 7 must be read from the program address while dq 6 can be read from any address. to resume the operation of sector erase, the resume command (30h) should be written. any further writes of the resume command at this point will be ignored. another erase suspend command can be written after the chip has resumed erasing. fast mode set/reset mbm29sl800te/be has fast mode function. this mode dispenses with the initial two unclock cycles required in the standard program command sequence by writing fast mode command into the command register. in this mode, the required bus cycle for programming is two cycles instead of four bus cycles in standard program command. the read operation is also executed after exiting this mode. during fast mode, do not write any commands other than the fast program/fast mode reset command. to exit this mode, it is necessary to write fast mode reset command into the command register. (refer to the embedded program tm algorithm for fast mode in n flow chart extended algorithm.) the v cc active current is required even ce = v ih during fast mode. fast programming during fast mode, the programming can be executed with two bus cycles operation. the embedded program algorithm is executed by writing program set-up command (a0h) and data write cycles (pa/pd) . (refer to the embedded program tm algorithm for fast mode in n flow chart extended algorithm.) extended sector protection in addition to normal sector protection, the mbm29sl800te/be has extended sector protection as extended function. this function enable to protect sector by forcing v id on reset pin and write a commnad sequence. unlike conventional procedure, it is not necessary to force v id and control timing for control pins. the only reset pin requires v id for sector protection in this mode. the extended sector protect requires v id on reset pin. with this condition, the operation is initiated by writing the set-up command (60h) into the command register. then, the sector addresses pins (a 18 , a 17 , a 16 , a 15 , a 14 , a 13 and a 12 ) and (a 6 , a 1 , a 0 ) = (0, 1, 0) should be set to the sector to be protected (recommend to set v il for the other addresses pins) , and write extended sector protect
mbm29sl800te/be -90/10 19 command (60h) . a sector is typically protected in 250 m s. to verify programming of the protection circuitry, the sector addresses pins (a 18 , a 17 , a 16 , a 15 , a 14 , a 13 and a 12 ) and (a 6 , a 1 , a 0 ) = (0, 1, 0) should be set and write a command (40h) . following the command write, a logical 1 at device output dq 0 will produce for protected sector in the read operation. if the output data is logical 0, please repeat to write extended sector protect command (60h) again. to terminate the operation, it is necessary to set reset pin to v ih . write operation status hardware sequence flags *1: successive reads from the erasing or erase-suspend sector causes dq 2 to toggle. *2: reading from non-erase suspend sector address will indicate logic 1 at the dq 2 bit. dq 7 data polling the mbm29sl800te/be devices feature data polling as a method to indicate to the host that the embedded algorithms are in progress or completed. during the embedded program algorithm an attempt to read the devices will produce the complement of the data last written to dq 7 . upon completion of the embedded program algorithm, an attempt to read the device will produce the true data last written to dq 7 . during the embedded erase algorithm, an attempt to read the device will produce a 0 at the dq 7 output. upon completion of the embedded erase algorithm an attempt to read the device will produce a 1 at the dq 7 output. the flowchart for data polling (dq 7 ) is shown in data polling algorithm in n flow chart. for chip erase and sector erase, the data polling is valid after the rising edge of the sixth we pulse in the six write pulse sequence. data polling must be performed at sector address within any of the sectors being erased and not a protected sector. otherwise, the status may not be valid. once the embedded algorithm operation is close to being completed, the mbm29sl800te/be data pins (dq 7 ) may change asynchronously while the output enable (oe ) is asserted low. this means that the devices are driving status information on dq 7 at one instant of time and then that bytes valid data at the next instant of time. depending on when the system samples the dq 7 output, it may read the status or valid data. even if the device has completed the embedded algorithm operation and dq 7 has a valid data, the data outputs on dq 6 to dq 0 may be still invalid. the valid data on dq 7 to dq 0 will be read on the successive read attempts. the data polling feature is only active during the embedded programming algorithm, embedded erase algorithm or sector erase time-out. (see hardware sequence flags.) status dq 7 dq 6 dq 5 dq 3 dq 2 in progress embedded program algorithm dq 7 toggle 0 0 1 embedded erase algorithm 0 toggle 0 1 toggle * 1 erase suspended mode erase suspend read (erase suspended sector) 1 1 0 0 toggle erase suspend read (non-erase suspended sector) data data data data data erase suspend program (non-erase suspended sector) dq 7 * 1 toggle * 1 001 * 2 exceeded time limits embedded program algorithm dq 7 toggle 1 0 1 embedded erase algorithm 0 toggle 1 1 n/a erase suspended mode erase suspend program (non-erase suspended sector) dq 7 toggle 1 0 n/a
mbm29sl800te/be -90/10 20 see data polling during embedded algorithm operation timing diagram in n timing diagram for the data polling timing specifications and diagrams. dq 6 toggle bit i the mbm29sl800te/be also feature the toggle bit i as a method to indicate to the host system that the embedded algorithms are in progress or completed. during an embedded program or erase algorithm cycle, successive attempts to read (oe toggling) data from the devices will result in dq 6 toggling between one and zero. once the embedded program or erase algorithm cycle is completed, dq 6 will stop toggling and valid data will be read on the next successive attempts. during programming, the toggle bit i is valid after the rising edge of the fourth we pulse in the four write pulse sequence. for chip erase and sector erase, the toggle bit i is valid after the rising edge of the sixth we pulse in the six write pulse sequence. the toggle bit i is active during the sector time out. in programming, if the sector being written to is protected, the toggle bit will toggle for about 2 m s and then stop toggling without the data having changed. in erase, the devices will erase all the selected sectors except for the ones that are protected. if all selected sectors are protected, the chip will toggle the toggle bit for about 100 s and then drop back into read mode, having changed none of the data. either ce or oe toggling will cause the dq 6 to toggle. in addition, an erase suspend/resume command will cause the dq 6 to toggle. see ac waveforms for toggle bit i during embedded algorithm operations in n timing diagram for the toggle bit i timing specifications and diagrams. dq 5 exceeded timing limits dq 5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count) . under these conditions dq 5 will produce a 1. this is a failure condition which indicates that the program or erase cycle was not successfully completed. data polling is the only operating function of the devices under this condition. the ce circuit will partially power down the device under these conditions (to approximately 2 ma) . the oe and we pins will control the output disable functions as described in mbm29sl800te/be user bus operations (byte = v ih ) and mbm29sl800te/be user bus operations (byte = v il ) in n device bus operation. the dq 5 failure condition may also appear if a user tries to program a non blank location without erasing. in this case the devices lock out and never complete the embedded algorithm operation. hence, the system never reads a valid data on dq 7 bit and dq 6 never stops toggling. once the devices have exceeded timing limits, the dq 5 bit will indicate a 1. please note that this is not a device failure condition since the devices were incorrectly used. if this occurs, reset the device with command sequence. dq 3 sector erase timer after the completion of the initial sector erase command sequence the sector erase time-out will begin. dq 3 will remain low until the time-out is complete. data polling and toggle bit are valid after the initial sector erase command sequence. if data polling or the toggle bit i indicates the device has been written with a valid erase command, dq 3 may be used to determine if the sector erase timer window is still open. if dq 3 is high (1) the internally controlled erase cycle has begun. if dq 3 is low (0) the device will accept additional sector erase commands. to insure the command has been accepted, the system software should check the status of dq 3 prior to and following each subsequent sector erase command. if dq 3 were high on the second status check, the command may not have been accepted. see hardware sequence flags.
mbm29sl800te/be -90/10 21 dq 2 toggle bit ii this toggle bit ii, along with dq 6 , can be used to determine whether the devices are in the embedded erase algorithm or in erase suspend. successive reads from the erasing sector will cause dq 2 to toggle during the embedded erase algorithm. if the devices are in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause dq 2 to toggle. when the devices are in the erase-suspended-program mode, successive reads from the byte address of the non-erase suspended sector will indicate a logic 1 at the dq 2 bit. dq 6 is different from dq 2 in that dq 6 toggles only when the standard program or erase, or erase suspend program operation is in progress. the behavior of these two status bits, along with that of dq 7 , is summarized as follows : for example, dq 2 and dq 6 can be used together to determine if the erase-suspend-read mode is in progress. (dq 2 toggles while dq 6 does not.) see also hardware sequence flags and dq 2 vs. dq 6 in n timing dia- gram. furthermore, dq 2 can also be used to determine which sector is being erased. when the device is in the erase mode, dq 2 toggles if this bit is read from an erasing sector. reading toggle bits dq 6 /dq 2 whenever the system initially begins reading toggle bit status, it must read dq 7 to dq 0 at least twice in a row to determine whether a toggle bit is toggling. typically a system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase operation. the system can read array data on dq 7 to dq 0 on the following read cycle. however, if, after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of dq 5 is high (see the section on dq 5 ) . if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as dq 5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. if it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially determines that the toggle bit is toggling and dq 5 has not gone high. the system may continue to monitor the toggle bit and dq 5 through successive read cycles, deter- mining the status as described in the previous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the begining of the algorithm when it returns to determine the status of the operation. (refer to toggle bit algorithm in n flow chart.) toggle bit status *1 : successive reads from the erasing or erase-suspend sector will cause dq 2 to toggle. *2 : reading from the non-erase suspend sector address will indicate logic 1 at the dq 2 bit. mode dq 7 dq 6 dq 2 program dq 7 toggle 1 erase 0 toggle toggle* 1 erase-suspend read (erase-suspended sector) 11toggle erase-suspend program dq 7 toggle 1* 2
mbm29sl800te/be -90/10 22 ry/by ready/busy the mbm29sl800te/be provide a ry/by open-drain output pin as a way to indicate to the host system that the embedded algorithms are either in progress or has been completed. if the output is low, the devices are busy with either a program or erase operation. if the output is high, the devices are ready to accept any read/write or erase operation. if the mbm29sl800te/be are placed in an erase suspend mode, the ry/by output will be high. during programming, the ry/by pin is driven low after the rising edge of the fourth we pulse. during an erase operation, the ry/by pin is driven low after the rising edge of the sixth we pulse. the ry/by pin will indicate a busy condition during the reset pulse. refer to ry/by timing diagram during program/erase operation timing diagram and reset , ry/by timing diagram in n timing diagram for a detailed timing diagram. the ry/by pin is pulled high in standby mode. since this is an open-drain output, the pull-up resistor needs to be connected to v cc ; multiples of devices may be connected to the host system via more than one ry/by pin in parallel. byte/word configuration the byte pin selects the byte (8-bit) mode or word (16-bit) mode for the mbm29sl800te/be devices. when this pin is driven high, the devices operate in the word (16-bit) mode. the data is read and programmed at dq 15 to dq 0 . when this pin is driven low, the devices operate in byte (8-bit) mode. under this mode, the dq 15 /a- 1 pin becomes the lowest address bit and dq 14 to dq 8 bits are tri-stated. however, the command bus cycle is always an 8-bit operation and hence commands are written at dq 7 to dq 0 and the dq 15 to dq 8 bits are ignored. data protection the mbm29sl800te/be are designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. during power up the devices automat- ically reset the internal state machine in the read mode. also, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command sequences. the devices also incorporate several features to prevent inadvertent write cycles resulting form v cc power-up and power-down transitions or system noise. if embedded erase algorithm is interrupted, there is possibility that the erasing sector (s) cannot be used. write pulse glitch protection noise pulses of less than 3 ns (typical) on oe , ce , or we will not initiate a write cycle. logical inhibit writing is inhibited by holding any one of oe = v il , ce = v ih , or we = v ih . to initiate a write cycle ce and we must be a logical zero while oe is a logical one. power-up write inhibit power-up of the devices with we = ce = v il and oe = v ih will not accept commands on the rising edge of we . the internal state machine is automatically reset to the read mode on power-up. sector protection device user is able to protect each sector individually to store and protect data. protection circuit voids both program and erase commands that are addressed to protected sectors. any commands to program or erase addressed to ptotected sector are ignored. (see sector ptotection in n functional description.)
mbm29sl800te/be -90/10 23 n absolute maximum ratings *1: voltage is defined on the basis of v ss = gnd = 0 v. *2: minimum dc voltage on input or i/o pins is - 0.3 v. during voltage transitions, input or i/o pins may undershoot v ss to - 2.0 v for periods of up to 20 ns. maximum dc voltage on input or i/o pins is v cc + 0.5 v. during voltage transitions, input or i/o pins may overshoot to v cc + 2.0 v for periods of up to 20 ns. *3: minimum dc input voltage on a 9 , oe and reset pins is - 0.3 v. during voltage transitions, a 9 , oe and reset pins may undershoot v ss to - 2.0 v for periods of up to 20 ns. voltage difference between input and supply voltage (v in - v cc ) does not exceed + 9.0 v. maximum dc input voltage on a 9 , oe and reset pins is + 11.5 v which may overshoot to + 12.5 v for periods of up to 20 ns. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n recommended operating conditions * : voltage is defined on the basis of v ss = gnd = 0v. note: operating ranges define those limits between which the proper device function is guaranteed. warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol rating unit min max storage temperature tstg - 55 + 125 c ambient temperature with power applied t a - 40 + 85 c voltage with respect to ground all pins except a 9 , oe , and reset * 1, * 2 v in , v out - 0.3 v cc + 0.5 v a 9 , oe , and reset * 1, * 3 v in - 0.3 + 11.5 v power supply voltage * 1 v cc - 0.5 + 3.0 v parameter symbol value unit min max ambient temperature t a - 40 + 85 c power supply voltage * v cc + 1.65 + 1.95 v
mbm29sl800te/be -90/10 24 n maximum overshoot/maximum undershoot 0.2 v cc - 0.3 v 20 ns - 2.0 v 20 ns 20 ns maximum undershoot waveform v cc + 0.5 v 0.8 v cc v cc + 2.0 v 20 ns 20 ns 20 ns maximum overshoot waveform 1 + 11.5 v v cc + 0.5 v + 12.5 v 20 ns 20 ns 20 ns maximum overshoot waveform 2 note : this waveform is applied for a 9 , oe , and reset .
mbm29sl800te/be -90/10 25 n dc characteristics *1: the i cc current listed includes both the dc operating current and the frequency dependent component. *2: i cc active while embedded algorithm (program or erase) is in progress. *3: automatic sleep mode enables the low power mode when address remain stable for 150 ns. *4: this timing is only for sector protection operation and autoselect mode. *5: applicable for only v cc applying. parameter symbol conditions value unit min typ max input leakage current i li v in = v ss to v cc , v cc = v cc max - 1.0 ?+ 1.0 m a output leakage current i lo v out = v ss to v cc , v cc = v cc max - 1.0 ?+ 1.0 m a a 9 , oe , reset inputs leakage current i lit v cc = v cc max, a 9 , oe , reset = 11 v ?? 35 m a v cc active current * 1 i cc1 ce = v il , oe = v ih , f = 10 mhz byte ?? 20 ma word 20 ce = v il , oe = v ih , f = 5 mhz byte ?? 10 ma word 10 v cc active current * 2 i cc2 ce = v il , oe = v ih ?? 25 ma v cc current (standby) i cc3 v cc = v cc max, ce = v cc 0.3 v, reset = v cc 0.3 v ? 15 m a v cc current (standby, reset) i cc4 v cc = v cc max, reset = v ss 0.3 v ? 15 m a v cc current (automatic sleep mode) * 3 i cc5 v cc = v cc max, ce = v ss 0.3 v, reset = v cc 0.3 v, v in = v cc 0.3 v or v ss 0.3 v ? 15 m a input low voltage v il ?- 0.3 ? 0.2 v cc v input high voltage v ih ? 0.8 v cc ? v cc + 0.3 v voltage for autoselect and sector protection (a 9 , oe , reset ) * 4, * 5 v id ? 10 10.5 11 v output low voltage v ol i ol = 0.1 ma, v cc = v cc min ?? 0.1 v output high voltage v oh i oh = - 100 m av cc - 0.1 ?? v
mbm29sl800te/be -90/10 26 n ac characteristics ? read only operations characteristics * : test conditions : output load : 30 pf input rise and fall times : 5 ns input pulse levels : 0.0 v or v cc timing measurement reference level input : v cc / 2 output : v cc / 2 parameter symbol test setup value * unit -90 -10 jedec standard min max min max read cycle time t avav t rc ? 90 ? 100 ? ns address to output delay t avqv t acc ce = v il oe = v il ? 90 ? 100 ns chip enable to output delay t elqv t ce oe = v il ? 90 ? 100 ns output enable to output delay t glqv t oe ?? 35 ? 35 ns chip enable to output high-z t ehqz t df ?? 30 ? 30 ns output enable to output high-z t ghqz t df ?? 30 ? 30 ns output hold time from addresses, ce or oe , whichever occurs first t axqx t oh ? 0 ? 0 ? ns reset pin low to read mode ? t ready ?? 20 ? 20 m s c l device under test test conditions note : c l = 30 pf including jig capacitance
mbm29sl800te/be -90/10 27 ? write / erase / program operations *1: this does not include the preprogramming time. *2: this timing is for sector protection operation. parameter symbol value unit -90 -10 jedec standard min typ max min typ max write cycle time t avav t wc 90 ?? 100 ?? ns address setup time t avwl t as 0 ?? 0 ?? ns address hold time t wlax t ah 45 ?? 50 ?? ns data setup time t dvwh t ds 45 ?? 50 ?? ns data hold time t whdx t dh 0 ?? 0 ?? ns output enable setup time ? t oes 0 ?? 0 ?? ns output enable hold time read ? t oeh 0 ?? 0 ?? ns toggle and data polling 10 ?? 10 ?? ns read recover time before write t ghwl t ghwl 0 ?? 0 ?? ns read recover time before write t ghel t ghel 0 ?? 0 ?? ns ce setup time t elwl t cs 0 ?? 0 ?? ns we setup time t wlel t ws 0 ?? 0 ?? ns ce hold time t wheh t ch 0 ?? 0 ?? ns we hold time t ehwh t wh 0 ?? 0 ?? ns write pulse width t wlwh t wp 45 ?? 50 ?? ns ce pulse width t eleh t cp 45 ?? 50 ?? ns write pulse width high t whwl t wph 30 ?? 30 ?? ns ce pulse width high t ehel t cph 30 ?? 30 ?? ns programming operation byte t whwh1 t whwh1 ? 10.6 ?? 10.6 ?m s word ? 14.6 ?? 14.6 ?m s sector erase operation * 1 t whwh2 t whwh2 ? 1.5 ?? 1.5 ? s v cc setup time ? t vcs 50 ?? 50 ??m s rise time to v id * 2 ? t vidr 500 ?? 500 ?? ns voltage transition time * 2 ? t vlht 4 ?? 4 ??m s write pulse width * 2 ? t wpp 100 ?? 100 ??m s oe setup time to we active * 2 ? t oesp 4 ?? 4 ??m s ce setup time to we active * 2 ? t csp 4 ?? 4 ??m s recover time from ry/by ? t rb 0 ?? 0 ?? ns reset pulse width ? t rp 500 ?? 500 ?? ns reset hold time before read ? t rh 200 ?? 200 ?? ns program/erase valid to ry/by delay ? t busy ?? 90 ?? 90 ns delay time from embedded output enable ? t eoe ?? 90 ?? 100 ns power on/off timing ? t ps 0 ?? 0 ?? ns erase time-out time ? t tow 50 ?? 50 ??m s erase suspend transition time ? t spo ?? 20 ?? 20 m s
mbm29sl800te/be -90/10 28 n erase and programming performance n pin capacitance tsop, fbga, csop pin capacitance notes : test conditions t a = + 25 c, f = 1.0 mhz dq 15 /a -1 pin capacitance is stipulated by output capacitance. parameter value unit remarks min typ max sector erase time ? 1.5 15 s excludes programming time prior to erasure word programming time ? 14.6 ?m s excludes system-level overhead byte programming time ? 10.6 300 m s chip programming time ? 7.7 200 s excludes system-level overhead program/erase cycle 100,000 ?? cycle parameter symbol test setup value unit typ max input capacitance c in v in = 07.59.5pf output capacitance c out v out = 0810pf control pin capacitance c in2 v in = 01013pf
mbm29sl800te/be -90/10 29 n timing diagram ? key to switching waveforms waveform inputs outputs must be steady may change from h to l may change from l to h "h" or "l": any change permitted does not apply will be steady will change from h to l will change from l to h changing, state unknown center line is high- impedance "off" state read operation timing diagram address address stable high-z high-z ce oe we outputs outputs valid t rc t acc t oe t df t ce t oh t oeh
mbm29sl800te/be -90/10 30 hardware reset/read operation timing diagram address ce reset outputs high-z outputs valid address stable t rc t acc t rh t rp t rh t ce t oh
mbm29sl800te/be -90/10 31 address data ce oe we 3rd bus cycle data polling 555h pa a0h pd dq 7 d out d out pa t wc t as t ah t rc t ce t whwh1 t wph t wp t ghwl t ds t dh t df t oh t oe t cs t ch alternate we controlled program operation timing diagram notes : pa is address of the memory location to be programmed. pd is data to be programmed at byte address. dq 7 is the output of the complement of the data written to the device. d out is the output of the data written to the device. figure indicates last two bus cycles out of four bus cycles sequence. these waveforms are for the 16 mode. (the addresses differ from 8 mode.)
mbm29sl800te/be -90/10 32 address data we oe ce 3rd bus cycle data polling 555h pa a0h pd dq 7 d out pa t wc t as t ah t whwh1 t cph t cp t ghel t ds t dh t ws t wh alternate ce controlled program operation timing diagram notes : pa is address of the memory location to be programmed. pd is data to be programmed at byte address. dq 7 is the output of the complement of the data written to the device. d out is the output of the data written to the device. figure indicates last two bus cycles out of four bus cycles sequence. these waveforms are for the 16 mode. (the addresses differ from 8 mode.)
mbm29sl800te/be -90/10 33 address data v cc ce oe we 555h 2aah 555h 555h 2aah sa* t wc t as t ah t cs t ghwl t ch t wp t ds t vcs t dh t wph aah 55h 80h aah 55h 10h/ 30h 10h for chip erase sa* 30h t tow chip/sector erase operation timing diagram * : sa is the sector address for sector erase. addresses = 555h (word) for chip erase. note : these waveforms are for the 16 mode. the addresses differ for 8 mode.
mbm29sl800te/be -90/10 34 t oeh t ch t oe t ce t df t busy t eoe t whwh1 or 2 ce dq 7 dq 6 to dq 0 ry/by dq 7 dq 7 = valid data dq 6 to dq 0 = outputs flag dq 6 to dq 0 valid data oe we high-z high-z data data * data polling during embedded algorithm operation timing diagram * : dq 7 = valid data (the device has completed the embedded operation) .
mbm29sl800te/be -90/10 35 t dh t oe t ce ce we oe dq 6 /dq 2 address ry/by data toggle data toggle data toggle data stop toggling outpu t valid * t busy t oeh t oeh t oeph t aht t aht t aso t as t ceph ac waveforms for toggle bit i during embedded algorithm operations * : dq 6 stops toggling (the device has completed the embedded operation) .
mbm29sl800te/be -90/10 36 ce ry/by we rising edge of the last we signal t busy entire programming or erase operations ry/by timing diagram during program/erase operation timing diagram t rp t rb t ready ry/by we reset reset , ry/by timing diagram
mbm29sl800te/be -90/10 37 t wpp t vlht t vlht t oe t csp t oesp t vcs t vlht t vlht a 18 , a 17 , a 16 a 15 , a 14 , a 13 a 12 a 6 , a 0 a 1 a 9 v cc oe v id v ih v id v ih we ce data spax 01h spay sector protection timing diagram spax : sector address to be protected spay : next sector address to be protected note : a- 1 is v il on byte mode.
mbm29sl800te/be -90/10 38 unprotection period t vlht t vlht t vcs t vlht t vidr program or erase command sequence v cc v id v ih we ry/by ce reset temporary sector unprotection timing diagram enter embedded erasing erase suspend erase resume enter erase suspend program erase suspend program erase complete erase erase suspend read erase suspend read erase dq 6 dq 2 * we toggle dq 2 and dq 6 with oe or ce dq 2 vs. dq 6 * : dq 2 is read from the erase-suspended sector.
mbm29sl800te/be -90/10 39 v cc we oe ce reset t wc t wc t vlht t vidr t vcs time-out sax sax say t wp t oe 60h 01h 40h 60h 60h data address a 6 , a 0 a 1 extended sector protection timing diagram sax : sector address to be protected say : next sector address to be protected time-out : time-out window = 250 m s (min)
mbm29sl800te/be -90/10 40 reset address data v cc t ps t ps t rh t acc 1.65 v 0 v input valid output valid 0 v power on/off timing diagram
mbm29sl800te/be -90/10 41 n flow chart embedded program tm algorithm note : the sequence is applied for 16 mode. the addresses differ from 8 mode. embedded algorithm tm 555h/aah 555h/a0h 2aah/55h program address/program data programming completed last address ? increment address verify data ? data polling program command sequence (address/command) : write program command sequence (see below) start no no yes yes embedded program algorithm in progress
mbm29sl800te/be -90/10 42 embedded erase tm algorithm note : the sequence is applied for 16 mode. the addresses differ from 8 mode. embedded algorithm tm 555h/aah 555h/80h 2aah/55h 555h/aah 555h/10h 2aah/55h 555h/aah 555h/80h 2aah/55h 555h/aah sector address /30h sector address /30h sector address /30h 2aah/55h erasure completed data = ffh ? data polling write erase command sequence (see below) start no yes embedded erase algorithm in progress chip erase command sequence (address/command) : individual sector/multiple sector erase command sequence (address/command) : additional sector erase commands are optional.
mbm29sl800te/be -90/10 43 data polling algorithm * : dq 7 is rechecked even if dq 5 = 1 because dq 7 may change simultaneously with dq 5 . va = valid address for programming = any of the sector addresses within the sector being erased during sector erase or multiple erases operation. = any of the sector addresses within the sector not being protected during sector erase or multiple sector erases operation. (data polling on sector group protected sector may fail.) dq 7 = data? dq 5 = 1? fail pass dq 7 = data? * read byte (dq 7 to dq 0 ) addr. = va read byte (dq 7 to dq 0 ) addr. = va start no no no yes yes yes
mbm29sl800te/be -90/10 44 toggle bit algorithm *1 : read toggle bit twice to determine whether it is toggling. *2 : recheck toggle bit because it may stop toggling as dq 5 changes to 1. dq 6 = toggle? dq 5 = 1? dq 6 = toggle? read (dq 7 to dq 0 ) addr. = v ih or v il read (dq 7 to dq 0 ) addr. = v ih or v il read dq 7 to dq 0 addr. = v ih or v il start no no no yes yes yes *1, *2 read dq 7 to dq 0 addr. = v ih or v il *1 fail pass
mbm29sl800te/be -90/10 45 start no no no yes yes yes data = 01h? device failed plscnt = 25? plscnt = 1 remove v id from a 9 write reset command remove v id from a 9 write reset command sector protection completed protect another sector? increment plscnt read from sector address addr. = spa, a 1 = v ih a 6 = a 0 = v il setup sector addr. (a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , a 12 ) oe = v id , a 9 = v id ce = v il , reset = v ih a 6 = a 0 = v il , a 1 = v ih activate we pulse time out 100 m s we = v ih , ce = oe = v il (a 9 should remain v id ) () * sector protection algorithm * : a- 1 is v il on byte mode.
mbm29sl800te/be -90/10 46 start perform erase or program operations reset = v id *1 reset = v ih temporary sector unprotection completed *2 temporary sector unprotection algorithm *1 : all protected sectors are unprotected. *2 : all previously protected sectors are protected once again.
mbm29sl800te/be -90/10 47 start no yes yes data = 01h? plscnt = 1 no no yes device failed plscnt = 25? remove v id from reset write reset command sector protection completed protect other sector? increment plscnt read from sector address (addr. = spa, a 0 = v il , a 1 = v ih , a 6 = v il ) remove v id from reset write reset command time out 150 m s reset = v id wait to 4 m s no yes setup next sector address device is operating in temporary sector unprotection mode to protect sector write 60h to secter address (a 6 = a 0 = v il , a 1 = v ih ) to verify sector protection write 40h to secter address (a 6 = a 0 = v il , a 1 = v ih ) to setup sector protection write xxxh/60h extended sector protection entry? extended sector protection algorithm
mbm29sl800te/be -90/10 48 555h/aah 555h/20h xxxh/90h xxxh/f0h xxxh/a0h 2aah/55h program address/program data programming completed last address ? increment address verify data? data polling start no no yes yes set fast mode in fast program reset fast mode embedded program tm algorithm for fast mode note : the sequence is applied for 16 mode. the addresses differ from 8 mode. fast mode algorithm
mbm29sl800te/be -90/10 49 n ordering information part no. package access time sector architecture mbm29sl800te-90pbt mbm29sl800te-10pbt 48-ball plastic fbga (bga-48p-m20) 90 100 top sector mbm29sl800te-90pw mbm29sl800te-10pw 45-ball plastic scsp (wlp-45p-m02) 90 100 mbm29sl800be-90pbt mbm29sl800be-10pbt 48-ball plastic fbga (bga-48p-m20) 90 100 bottom sector mbm29sl800be-90pw MBM29SL800BE-10PW 45-ball plastic scsp (wlp-45p-m02) 90 100 10 e t mbm29sl800 device number/description mbm29sl800 8 mega-bit (1 m 8-bit or 512 k 16-bit) cmos flash memory 1.8 v-only read, program, and erase package type pbt = 48-ball fine pitch ball grid array package (fbga) pw = 45-ball super chip size package (scsp) speed option see product selector guide device revision boot code t = top sector b = bottom sector pbt
mbm29sl800te/be -90/10 50 n package dimensions (continued) 48-ball plastic fbga (bga-48p-m20) dimensions in mm (inches). note : the values in parentheses are reference values. c 2003 fujitsu limited b48020s-c-2-2 8.00 0.20(.315 .008) 0.38 0.10(.015 .004) (stand off) (mounting height) 6.00 0.20 (.236 .008) 0.10(.004) 0.80(.031)typ 5.60(.220) 4.00(.157) 48- ? 0.45 0.05 (48- ? .018 .002) m ? 0.08(.003) h g fed c ba 6 5 4 3 2 1 .043 C .005 +.003 C 0.13 +0.12 1.08 (index area)
mbm29sl800te/be -90/10 51 (continued) 45-ball plastic scsp (wlp-45p-m02) dimensions in mm (inches). note : the values in parentheses are reference values. c 2004 fujitsu limited w45002sc-1-1 4.70 0.10 3.54 0.10 (.139 .004) (laser marking) 0.08(.003) z (0.50x8=4.00) 0.50(.020) typ 0.50(.020) typ 45- ? 0.23 0.10 (45- ? .009 .004) m 0.08(.003) z 4- ? 0.13(4- ? .005) x y index area 0.10(.004) min 0.80(.032) ((.020x8=.158)) (0.50x4=2.00) ((.020x4=.079)) xyz max (.185 .004) (stand off)
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